Chapter 13: Troubleshooting
13–7
Troubleshooting Issues
You can avoid these problems by inserting a Non-synthesizable Output block
followed immediately by a Non-synthesizable Input block. This combination
functions as a temporary input terminator and you can remove them after you debug
your design.
A Specified Path Cannot be Found or a File Name is Too Long
The maximum length for a path is limited to 256 characters in the Windows operating
system.
When the file path to a model or the name of the model is very long, DSP Builder may
attempt to create a file path exceeding this limit.
If this problem occurs, reduce the length of the file path to the model or the length of
its name.
Incorrect Interpretation of Number Format in Output from MegaCore
Functions
For some MegaCore functions, DSP Builder may be unable to infer whether it should
interpret output signals as signed, unsigned, signed fractional. This issue can cause
problems when visualizing the output. For example, by directly attaching scopes,
when the signal waveform may obscur because of the incorrectly inferred number
formats.
Correct this issue by connecting to the output with an AltBus block or a
Non-synthesizable Output block (as appropriate) with the correct bus type
assignment.
Simulation Mismatch For FIR Compiler MegaCore Function
FIR Compiler MegaCore function-generated functional simulation models generally
do not output valid data until the data storage of these models is clear.
f For more information including a formula that estimates the number of cycles before
relevant samples are available, refer to the Simulate the Design section in the FIR
Compiler User Guide .
Simulation Mismatch After Changing Signals or Parameters
The simulation results may not match after changing any signal names or parameters.
If this problem occurs, delete the previous testbench directory ( tb_< model name > )
and run the simulation again.
Unexpected Exception Error when Generating Blocks
DSP Builder issues errors of the following form when you generate a DSP Builder
system:
Info: IP Generator Info: stderr: No clock info for
my_alt_dspbuilder_clock
Info: IP Generator Info: stderr: Failed to find clock
my_alt_dspbuilder_clock
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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IP-TRIETHERNETF 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
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